1. Field of the Invention
The present invention relates to a semiconductor memory such as a ROM (read only memory) and an EEPROM (electrically erasable programmable ROM) having a number of memory cells arranged in the form of a matrix, and more specifically to a semiconductor memory required to precharge a memory cell array at the time of reading a cell data.
2. Description of Related Art
In this type of semiconductor memory required to carrying out a precharge at the time of reading a cell data, it is a general practice to precharge bit lines of the cell array. This precharge is performed for a bit line diffused interconnection of each memory cell. When a reading is carried out, virtual ground lines are discharged, so that the diffused interconnection connected to a selected virtual ground line is discharged.
Referring to FIG. 6, there is shown a circuit diagram of this type of semiconductor memory in the prior art. In FIG. 6, Reference Signs D1 to D3 designate bit line terminals each connected to a not-shown sense amplifier, and Reference Signs WS1 to WSn denote word lines. Reference Signs BS1 to BS6 indicate bank selection lines, and Reference Signs VG1 to VG4 show virtual ground line terminals. Reference Signs BT1 to BT6 designate bank selection transistors, and Reference Sign SARY denotes a memory cell array. This memory cell array SARY includes a number of memory cells, which are arranged in the form of a matrix, and some of which are designated with Reference Signs SX1, SX2, SY1 to SY8.
In the semiconductor memory shown in FIG. 6, when data is read out from the memory cell SX1, a sense amplifier current is supplied to the bit line terminal D1 from the sense amplifier, and a corresponding upper side bank selection line(s) BS is selected to turn on the bank selection transistors BT connected to the selected bank selection line(s) BS, so that the sense amplifier current is supplied through an internal bit line diffused interconnection 1 (first sub-bit line) to a drain of a selected memory cell SX1. On the other hand, one row of memory cells including the memory cell SX1 are selected by the word line WSn, and a corresponding lower side bank selection(s) line BS is selected to turn on the bank selection transistors BT connected to the selected bank selection line(s) BS, so that data is read out from a source of the selected memory cell SX1 through an internal bit line diffused interconnection 2 (second sub-bit line) and the virtual ground line terminal VG1. At this time, the bit line terminal D2 and the virtual ground line terminal VG2 positioned at a drain side of the selected memory cell SX1 have been precharged.
Referring to FIG. 7, there is shown a circuit diagram of the semiconductor memory disclosed in Japanese Patent Application Pre-examination Publication No. JP-A-4-311900 and its corresponding U.S. Pat. No. 5,268,861 (the content of which is incorporated by reference in its entirety into this application). In FIG. 7, elements similar to those shown in FIG. 6 are given the same Reference Signs, and explanation thereof will be omitted for simplification of the description.
This semiconductor memory is so configured that two bank selection lines BS1 and BS2 are located at an upper side of the memory cell array SARY, and two bank selection lines BS3 and BS4 are located at a lower side of the memory cell array SARY. Two bit line diffused interconnections 1 are connected through the bank selection transistors BT1 and BT2 to one bit line terminal D and each of the bit line diffused interconnections 1 is connected to a drain of memory cells included in a pair of adjacent columns in the memory cell array SARY, and two bit line diffused interconnections 2 are connected through the bank selection transistors BT3 and BT4 to one virtual ground line terminal VG and each of the bit line diffused interconnections 2 is connected to a source of memory cells included in a pair of adjacent columns in the memory cell array SARY.
In the prior art semiconductor memory circuit shown in FIG. 6, when data is read out from the memory cell SX1 in an ON condition, if an adjacent memory cell SX2 is in an ON condition, a sense amplifier current 1 from the bit line terminal D1 and a circulating current 2 from the precharged virtual ground line VG2, are supplied to the drain of the memory cell SX1. Here, when the selected memory cell SX1 is positioned remote from the bit line terminal D1 but near to the virtual ground line VG2, assuming that the resistance of the whole of the bit line diffused interconnections in one path from the bit line terminal D to the virtual ground line terminal VG is "R" as shown in an equivalent circuit shown in FIG. 8, the resistance "R-R1" of the bit line diffused interconnection 2 from the virtual ground line VG2 is smaller than the resistance "RR1" of the bit line diffused interconnection 1 from the bit line terminal D1, and therefore, the circulating current 2 becomes larger than the sense amplifier current 1. As a result, a sufficient sense amplifier current does not flow through the selected sense amplifier SX1, and therefore, when the data is read out at the virtual ground line terminal VG1, an erroneous data is read out. This is a problem. Furthermore, when data is read from the memory cell SX1 in the ON condition, since three transistors BT2, BT4 and BT6 exist between the bit line terminal D1 and the virtual ground line terminal VG1, the sense amplifier current lowers, with the result that an erroneous data is read out. This is also a problem.
In addition, for example, when data is read out from the memory cell SY1, the sense amplifier current is supplied to the bit line terminal D2, and data is read from the virtual ground line terminal VG2. At this time, the bit line terminal D3 and the virtual ground line terminal VG3 are precharged. In this case, assuming that the memory cells SY1 and SY8 are in an OFF condition and the memory cells SY2 to SY7 are in an ON condition, since a precharge current 5 from the virtual ground line VG3 is cut off at the memory cell SY8, diffused layers "A" to "F" must be charged with a sense amplifier current 4 from the bit line terminal D2. Therefore, the time constant at the data reading time becomes large, with the result that a data reading speed becomes low. This is also a problem.
On the other hand, the prior art semiconductor memory shown in FIG. 7 can solve, at some degree, the problems of the data erroneous reading and the lowered data reading speed in the prior art semiconductor memory shown in FIG. 6. However, since the bank selection is in the four-stage construction, the prior art semiconductor memory shown in FIG. 7 cannot be applied to a bank selection construction having more than four stages.
In general, in a semiconductor memory, a drain and a source of each memory cell are formed of a diffused layer similar to the internal bit line diffused interconnections 1 and 2, and a gate of each memory cell is formed of a polysilicon. In addition, a drain and a source of each bank selection transistor are formed of a diffused layer, and a gate of each bank selection transistor is formed of a polysilicon. The word lines and the bank selection lines connected to the gate of the memory cells and the gate of the bank selection transistors are formed of a polysilicon. Namely, in FIG. 9 illustrating a layout of the prior art semiconductor memory shown in FIG. 7, "BN" shows a diffused layer such as the bit line diffused interconnection, and "WS" indicates a polysilicon such as the word line. "Al" denotes an aluminum interconnection connected to the bit line terminal D or the virtual ground line terminal VG.
Here, as shown in FIG. 9, a minimum width of the diffused layer BN has a limit of 0.5 .mu.m, and a minimum spacing between adjacent diffused layers BN has a limit of 0.5 .mu.m Therefore, a minimum locating pitch of the diffused layers BN has a limit of 1.0 .mu.m
In the prior art semiconductor memory shown in FIG. 7, for the bit line terminals and the virtual ground line terminals, it is necessary to provide one aluminum interconnection for each two diffused layers. Therefore, even if it is attempted to increase the integration density by minimizing the locating pitch of the diffused layers BN, the integration density is limited by the locating pitch of the aluminum interconnections. Namely, assuming that the minimum locating pitch of the diffused layers BN is 1.0 .mu.m, the locating pitch of the aluminum interconnection "Al" connected to either the bit line terminal D or the virtual ground line terminal VG, becomes 2.0 .mu.m, as shown in FIG. 9. This means that the line width and the locating spacing of the aluminum interconnection "Al" become 1 .mu.m. Under this condition, it is difficult to locate and pattern the aluminum interconnection.